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• so-logic
  • Iletişim ve Yerimiz
    • so-logic Brasil2015-03-20 13:02:34 +0100
    • So-logic Sirbistan2009-07-23 12:21:56 +0200
  • Tarih2016-08-24 16:09:39 +0200
  • Iletişim ağ
    • Dağıtım 2019-07-18 11:00:26 +0200
    • Eğitim2019-10-31 11:37:15 +0100
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  • Işten sonra
    • Hoteller2019-07-11 09:28:18 +0200
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    • Kültürel mekanlar2019-07-11 09:20:36 +0200
  • Resimler
    • PCB2015-03-27 14:42:05 +0100
    • Ayi Resimleri2015-03-27 14:44:27 +0100
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• Hizmetlerimiz
  • Development2016-08-24 14:11:00 +0200
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  • Reviews2016-08-24 14:14:25 +0200
  • Feasibility studies2016-08-24 14:16:52 +0200
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  • Network2016-08-24 14:19:13 +0200
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  • Webservice2016-08-24 14:21:48 +0200
• Temel Bilgiler
  • FPGA universe
    • Tutorials
      • Basic FPGA Tutorial - Vivado v2014.4, VHDL2015-03-20 13:59:58 +0100
      • Basic FPGA Tutorial - Vivado v2014.4, Verilog2015-03-20 14:14:32 +0100
      • Basic FPGA Tutorial - ISE v14.7, VHDL2015-03-20 14:15:39 +0100
      • Basic Embedded System Design Tutorial - Vivado v2014.4, C2015-03-20 14:19:53 +0100
      • Basic HLS Tutorial v2024.1
      • Basic SystemC Tutorial v2021.1
      • Basic Functional Verification Tutorial v2024.1
      • VHDL Style Guide2015-04-10 16:12:20 +0200
  • Links
    • Elektronik2015-04-10 16:12:27 +0200
    • FPGA2016-08-24 16:43:48 +0200
    • Faydali olabiir genel bilgi Avusturya ve Viyana2016-08-24 16:44:08 +0200
  • Hızlı referans kılavuzları2015-04-10 16:12:29 +0200
  • Newsletters
    • Newsletter - September 2016
    • Newsletter - February 2016
    • Newsletter - November 2015
    • Newsletter - April 20152015-04-10 16:12:34 +0200
    • Newsletter - March 20152015-04-10 16:12:33 +0200
• Kurslar
  • Xilinx
    • AI
      • Designing with Versal AI Engine 1: Architecture and Design Flow
      • Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
      • Designing with Versal AI Engine 3: Kernel Programming and Optimization
      • Developing AI Inference Solutions with the Vitis AI Platform
    • Architecture
      • Versal
        • Designing with the Versal Adaptive SoC: Architecture
        • Designing with the Versal Adaptive SoC: Design Methodology
        • Designing with the Versal Adaptive SoC: Power and Board Design
        • Designing with the Versal Adaptive SoC: Memory Interfaces
        • Designing with the Versal Adaptive SoC: Hardware Debug
      • Designing with the UltraScale Architecture2015-04-10 16:25:25 +0200
      • Designing with Xilinx 7 Series Families2015-04-10 16:17:57 +0200
      • Legacy
        • Spartan-6 and Virtex-6 ailesiyle dizayn etmek2009-12-04 13:59:03 +0100
        • Spartan-6 with ISE Migration to 7 Series with Vivado
        • Virtex-5 LX , SX LXT, SXT Platform FPGA ile dizayn etmek2009-12-04 14:18:05 +0100
        • Virtex-4 Family ile dizayn etmek2009-12-04 14:26:48 +0100
      • Versal Live Online Workshop Compendium Complete
        • AMD Versal Compendium 1 : Architecture
        • AMD Versal Compendium 2 : High Speed Communication
        • AMD Versal Compendium 3 : AI Engine
    • Bağlantı
      • Designing with the Versal Adaptive SoC: Serial Transceivers
      • Designing with the Versal Adaptive SoC: PCI Express Systems
      • Designing with the Versal Adaptive SoC: Network on Chip
      • Designing with the Zynq UltraScale+ RFSoC
      • How to Design a High-Speed Memory Interface2015-04-10 16:18:03 +0200
      • PCIe Protocol Overview2015-04-10 16:18:05 +0200
      • LogiCORE PCI Express System dizayn etmek2009-12-04 14:40:00 +0100
      • Multi-Gigabit Serial I/O ile dizayn etmek2009-12-07 13:35:03 +0100
      • Gigabit Ethernet2009-12-07 13:48:19 +0100
      • Xilinx FPGA için Signal Integrity ve Board Dizayn2009-12-15 15:28:00 +0100
      • Designing with AMD Xilinx Serial Transceivers
    • DSP
      • High-Level Synthesis with Vitis HLS
      • Vitis Model Composer: A MATLAB and Simulink-based Product
      • C++ for Adaptive SOC
      • Xilinx FPGA için DSP Uygulama Teknikleri2009-12-07 14:11:46 +0100
      • Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework
    • Embedded
      • Adaptive SoCs for System Architects
      • Embedded Heterogeneous Design
      • Operating Systems and Hypervisors in Adaptive SoCs
      • Zynq UltraScale+ MPSoC: Boot and Platform Management
      • Zynq UltraScale+ MPSoC for the Hardware Designer
      • Zynq All Programmable SoC System Architecture2015-04-10 16:22:52 +0200
      • Migrating to the Vitis Unified IDE
      • Embedded Design with PetaLinux Tools2015-04-10 16:23:00 +0200
      • Embedded Systems Development2009-12-14 14:10:57 +0100
      • Embedded Systems Software Development2009-12-14 14:22:23 +0100
      • Accelerating Applications with the Vitis Unified Software Environment
    • HDL
      • VHDL ile dizayn etmek2009-12-15 09:50:49 +0100
      • Advanced VHDL2009-12-15 10:11:08 +0100
      • Verilog ile dizayn etmek2009-12-15 10:03:34 +0100
      • Designing with System Verilog2015-04-10 16:23:14 +0200
      • Verification with System Verilog2015-04-10 16:23:15 +0200
    • Tools
      • Designing with the IP Integrator Tool
      • Designing FPGAs Using the Vivado Design Suite 1
      • Designing FPGAs Using the Vivado Design Suite 2
      • Designing FPGAs Using the Vivado Design Suite 3
      • Designing FPGAs Using the Vivado Design Suite 4
      • UltraFast Design Methodology2015-04-10 16:23:24 +0200
      • Design Closure Techniques
      • DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
  • Doulos
  • Mathworks
    • MATLAB Grundlagen2015-04-10 16:12:42 +0200
    • Machine Learning mit MATLAB
    • MATLAB Programmiertechniken2015-04-10 16:12:47 +0200
    • Programmierung von AMD Xilinx Zynq SoCs mit MATLAB und Simulink
    • Simulink zur System- und Algorithmenmodellierung2015-04-10 16:12:49 +0200
    • Signalverarbeitung mit Simulink
    • Objektorientierte Programmierung mit MATLAB
  • National Instruments
  • so-logic
    • Design Compendium Yocto for AMD Xilinx devices
    • Design Compendium Embedded System for AMD Xilinx devices
    • Design Compendium Verification for AMD Xilinx devices
    • Design Compendium VHDL for AMD Xilinx devices
    • Design Compendium System Verilog for AMD Xilinx devices
    • Design Compendium High Level Synthesis for AMD Xilinx devices
    • Design Compendium High Level SystemC for AMD Xilinx devices
    • High Level Synthesis
      • C++2015-04-10 16:17:45 +0200
      • SystemC TLM2015-04-10 16:17:47 +0200
      • SystemC Concepts2015-04-10 16:17:48 +0200
  • Ödeme koşulları 2016-08-25 13:50:41 +0200
  • Talimat 2016-08-25 12:55:37 +0200
• IP´s
  • Interface Cores
    • Ethernet
      • 10/100/1000 Mb/s Ethernet
        • 10/100/1000 Mb/s MAC Controller Core2015-04-10 16:25:42 +0200
        • 1000BASE-X PCS Core2015-04-10 16:25:43 +0200
        • 10/100/1000 Mb/s MAC Configurator Core
        • Ethernet GMII Core
        • Ethernet GMII2MII Core
        • Ethernet GMII2RGMII Core
      • 10G Ethernet
        • 10G MAC Controller Core2015-04-10 16:25:51 +0200
        • 10GBASE-R PCS Core2015-04-10 16:25:53 +0200
        • 10 Gb/s Ethernet MAC Configurator Core
      • Utility Ethernet Cores
        • Ethernet Pause Generator Core
        • Generator Checker Core
      • Encryption Ethernet Cores
        • AES Core
      • Miscellaneous Ethernet Cores
        • ARP Decoder Core
        • ARP Encoder Core
        • ARP Packet Core
        • ARP Table Core
        • Capture Register Core
        • Error Statistics Core
        • Ethernet Encoder Core
        • Ethernet Decoder Core
        • ICMP Decoder Core
        • ICMP Encoder Core
        • IP Decoder Core
        • IP Encoder Core
        • Ethertype2dest Core
        • Network Packet FIFO Core
        • Port2tdest Core
        • Protocol2tdest Core
        • Tdest2ethertype Core
        • Tdest2port Core
        • Protocol2protocol Core
        • Time Stamp Counter Core
        • UDP Decoder Core
        • UDP Encoder Core
        • UDP Register Handler Core
    • Serial ATA
      • SATA-II Host Controller Core2015-04-10 16:25:56 +0200
      • SATA-III Host Controller Core2015-04-10 16:25:57 +0200
  • Machine Learning Cores
    • Ensemble Classifiers Cores
      • Ensemble Inference Cores
        • Decision Tree Ensemble Inference Core2015-04-10 16:26:09 +0200
      • Ensemble Evaluation Cores
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture2015-04-10 16:26:13 +0200
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture2015-04-10 16:26:15 +0200
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture2015-04-10 16:26:16 +0200
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture2015-04-10 16:26:18 +0200
      • Combination Rules Cores
        • Behavior Knowledge Space Core - Parallel Architecture2015-04-10 16:26:21 +0200
        • Behavior Knowledge Space Core - Serial Architecture2015-04-10 16:26:23 +0200
        • Weighted Majority Voting Core - Parallel Architecture2015-04-10 16:26:28 +0200
        • Majority Voting Core - Parallel Architecture2015-04-10 16:26:29 +0200
        • Majority Voting Core - Serial Architecture2015-04-10 16:26:31 +0200
    • Decision Trees Cores
      • Decision Tree Inference Core2015-04-10 16:26:35 +0200
      • Decision Tree Core using Serial Architecture2015-04-10 16:26:37 +0200
      • Decision Tree Core using Pipelined Architecture2015-04-10 16:26:39 +0200
  • İşlemci Cores
    • 8051 Microcontroller Cores2015-04-10 16:27:01 +0200
  • Finished and IP Cores Under Development2015-03-20 14:35:13 +0100
• Mūşteriler