Site map
- so-logic
- Kontakt & Anreise
- so-logic Brasil
- so-logic Serbia2019-07-19 09:38:49 +0200
- Geschichte2015-01-13 18:13:50 +0100
- Networking
- Xilinx-Vertriebe2022-07-15 13:44:02 +0200
- Bildungseinrichtungen2019-10-31 11:36:19 +0100
- Partners2022-07-15 13:53:03 +0200
- Kooperationen2022-07-15 13:58:38 +0200
- Mitarbeiter2024-09-13 11:43:31 +0200
- Erholung & Fun
- Hotels2022-07-15 13:01:25 +0200
- Restaurants2022-07-15 13:32:33 +0200
- Bars & Cafés2019-07-11 10:56:10 +0200
- Culture2019-07-11 09:19:18 +0200
- Gallery
- Privacy and Policy2019-07-19 09:32:33 +0200
- Kontakt & Anreise
- sozius
- Aktivitäten
- Entwicklung2009-11-23 14:44:07 +0100
- Coaching - Consulting2009-11-23 14:55:15 +0100
- Review2009-11-23 15:08:54 +0100
- Machbarkeitsstudie2009-11-23 15:14:28 +0100
- Prototyping2014-05-26 14:59:33 +0200
- Netzwerk2009-11-23 15:44:38 +0100
- Hosting2009-11-23 15:51:41 +0100
- Web services2009-11-23 15:56:10 +0100
- Wissensbasis
- FPGA Universum
- Links
- Electronic
- FPGA
- Useful2019-07-04 09:54:31 +0200
- Quick reference guides
- Newsletters
- Trainings
- Xilinx
- AI
- Architecture
- Connectivity
- Designing with the Versal Adaptive SoC: Serial Transceivers
- Designing with the Versal Adaptive SoC: PCI Express Systems
- Designing with the Versal Adaptive SoC: Network on Chip
- Designing with the Zynq UltraScale+ RFSoC2019-11-04 14:04:50 +0100
- How to Design a High-Speed Memory Interface
- PCIe Protocol Overview
- Designing a LogiCORE PCI Express System
- Designing with Multi-Gigabit Serial I/O
- Gigabit Ethernet
- Signal Integrity and Board Design for AMD Xilinx FPGAs
- DSP
- Embedded
- Adaptive SoCs for System Architects
- Embedded Heterogeneous Design
- Operating Systems and Hypervisors in Adaptive SoCs
- Zynq UltraScale+ MPSoC: Boot and Platform Management
- Zynq UltraScale+ MPSoC for the Hardware Designer
- Zynq All Programmable SoC System Architecture
- Migrating to the Vitis Unified IDE
- Embedded Design with PetaLinux Tools
- Embedded Systems Development
- Embeded Systems Software Development
- Accelerating Applications with the Vitis Unified Software Environment
- HDL
- Tools
- Designing with the IP Integrator Tool
- Designing FPGAs Using the Vivado Design Suite 1
- Designing FPGAs Using the Vivado Design Suite 2
- Designing FPGAs Using the Vivado Design Suite 3
- Designing FPGAs Using the Vivado Design Suite 42019-07-09 14:23:52 +0200
- UltraFast Design Methodology
- Design Closure Techniques
- DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
- Doulos
- Mathworks
- National Instruments
- So-logic
- Design Compendium Yocto for AMD Xilinx devices
- Design Compendium Embedded System for AMD Xilinx devices
- Design Compendium Verification for AMD Xilinx devices
- Design Compendium VHDL for AMD Xilinx devices
- Design Compendium System Verilog for AMD Xilinx devices
- Design Compendium High Level Synthesis for AMD Xilinx devices
- Design Compendium High Level SystemC for AMD Xilinx devices
- High Level Synthesis
- Zahlungsbedingungen2010-01-04 15:38:16 +0100
- Anleitung2008-12-11 09:26:36 +0100
- Xilinx
- IPs
- Interface Cores
- Ethernet
- 10/100/1000 Mb/s Ethernet
- 10G Ethernet
- Utility Ethernet Cores
- Encryption Ethernet Cores
- Miscellaneous Ethernet Cores
- ARP Decoder Core
- ARP Encoder Core
- ARP Packet Core
- ARP Table Core
- Capture Register Core
- Error Statistics Core
- Ethernet Encoder Core
- Ethernet Decoder Core
- ICMP Decoder Core
- ICMP Encoder Core
- IP Decoder Core
- IP Encoder Core
- Ethertype2dest Core
- Network Packet FIFO Core
- Port2tdest Core
- Protocol2tdest Core
- Tdest2ethertype Core
- Tdest2port Core
- Protocol2protocol Core
- Time Stamp Counter Core
- UDP Decoder Core
- UDP Encoder Core
- UDP Register Handler Core
- Serial ATA
- Ethernet
- Machine Learning Cores
- Ensemble Classifiers Cores
- Ensemble Inference Cores
- Ensemble Evaluation Cores
- Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture
- Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture
- Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture
- Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture
- Combination Rules Cores
- Decision Trees Cores
- Ensemble Classifiers Cores
- Processor and Microcontroller Cores
- Finished and IP Cores Under Development
- Interface Cores
- Kunden