Miscellaneous Ethernet Cores |
So-Logic's solution to the Miscellaneous Ethernet consists from following cores:
- ARP Decoder Core
- ARP Encoder Core
- ARP Packet Core
- ARP Table Core
- Capture Register Core
- Error Statistis Core
- Ethernet Decoder Core
- Ethernet Encoder Core
- Ethertype2dest Core
- Generator Checker Raw Core
- Generator Checker Raw Stream2UDP Core
- Global Registers Core
- ICMP Decoder Core
- ICMP Encoder Core
- IP Decoder Core
- IP Encoder Core
- Network Packet FIFO Core
- Port2tdest Core
- Protocol2tdest Core
- Stream2UDP Core
- Tdest2ethertype Core
- Tdest2port Core
- Protocol2protocol Core
- Time Stamp Counter Core
- UDP Decoder Core
- UDP Encoder Core
- UDP Register Handler Core
ARP Decoder Core decodes ARP packets by checking and removing HTYPE, PTYPE, HLEN, PLEN and OPER. Only if the header is as expected, the packet is redirected.
ARP Encoder Core encodes ARP packets by prepending HTYPE, PTYPE, HLEN, PLEN, OPER to SHA, SPA, THA and TPA.
ARP Packet Core provides the host IP and MAC from the APR-request while filling in the EB8200 IP and MAC as provided from the input ports.
ARP Table Core saves and provides the APR entries.
Capture Register Core is a register file of a single capture interface of the EB8200. The basis for the implementation of the Global Register core.
Error Statistics Core is a error handler to keep track of certain errors in the design and output statistic counters.
Ethernet Decoder Core decodes sub-Ethernet frames from the MAC-core, by removing DA, SA and setting L/T (Ethertype/Length) constant during frame transmission.
Ethernet Encoder Core encodes ARP packets by prepending HTYPE, PTYPE, HLEN, PLEN, OPER to SHA, SPA, THA and TPA.
Ethertype2dest Core sets the m_axis_tdest signal according to the ethertype input. This input usually originates from the Ethernet encoder.
Generator Checker Raw Core
Generator Checker Raw Stream2UDP Core
Global Registers Core
ICMP Decoder Core decodes received ICMP packets, for exmaple PING.
ICMP Encoder Core encodes received ICMP packets, for exmaple PING.
IP Decoder Core decodes the iPv4 header and compares the calculated checksum with the header checksum. The IP Decoder only pass through valid bytes in case if the MAC core adds padding to the frame.
IP Encoder Core adds the IPv4 packet header which consists of 14 field (20 bytes) and calculates the header checksum.
Network Packet FIFO Core stores an incoming datastream in a conventional packet FIFO, but it also keeps track of the packet lengths of the individual packets.
Port2tdest Core sets the m_axis_tdest signal according to the port input. This input usually originates from the UDP decoder.
Porotocol2tdest Core sets the m_axis_tdest signal according to the protocol input. This input usually originates from the IP decoder.
Stream2UDP Core
Tdest2ethertype Core sets the ethertype output signal according to the s_axis_tdest input. This input usually originates from the stream interconnect where all the different protocol encoder are connected to rtype for details.
Tdest2port Core sets the port output signal according to the s_axis_tdest input. This input usually originates from the user cores that want to send UDP datagrams.
Protocol2protocol Core sets the protocol output signal according to the s_axis_tdest input. This input usually originates from the user cores that want to send IP packets.
Time Stamp Counter Core emulates time stamp.
UDP Decoder Core removes the header from the incoming UDP Packet. No CRC is performed and the length field is also ignored since it is wrong in case padding is already removed by the IP Core.
UDP Encoder Core prepends the header from the incoming UDP Packet. Since the CRC is not required, its field will be filled with 0x00. The source and destination port is set according to the input vectors.
UDP Register Handler Core is used to access the register file (connected with AXI-Light) with UDP Datagrams.