SystemC TLM

Description

Transaction-level modeling (TLM) is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. Communication mechanisms such as busses or FIFOs are modeled as channels, and are presented to modules using SystemC interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers - what data are transferred to and from what locations - and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus though the common interface.

However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in system level language and modeling domain

Training Duration

2 days

Who Should Attend?

FPGA designers interested in FPGA design high level system description for verification and implementation

Prerequisites

• Programming Skills in C/C++
• Solid understanding of embedded programming
• Intermediate HDL knowledge (VHDL or Verilog)
• Solid digital design background

Description

Transaction Level Modeling is being used in the industry to solve a variety of practical problems during the design, development and deployment of electronic systems. These problems include:
• Providing an early platform for software development
• Aiding software/hardware integration
• Enabling software performance analysis
• System Level Design architecture analysis
• Functional hardware verification

Topics

• Generic TLM APIs and data structures for transaction execution
• Interoperable Memory Mapped Bus (API + data + protocol semantics) for loosely-timed and approx-timed coding styles
• Support for non-intrusive/debug transactions
• Support for unobtrusively monitoring or probing transaction activity (Analysisports)
• Recommendations on common data-types
• Direct-memory interface
• Model synchronization