Training schedules 2025-01-14 - 2026-01-14
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
20.01. - 20.01.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
21.01. - 22.01.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
23.01. - 24.01.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.01. - 31.01.2025 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.01. - 29.01.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
29.01. - 30.01.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.02. - 10.02.2025 09:00-16:00 | C++ for Adaptive SOC | Xilinx | Virtual Learning Environment (Online) | € 0.00 | |
12.03. - 12.03.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
31.03. - 04.04.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
01.04. - 02.04.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.04. - 04.04.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
04.04. - 08.04.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
07.04. - 09.04.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
08.04. - 08.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.04. - 11.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.04. - 17.04.2025 09:00-17:00 | Designing with VHDL | Xilinx | Virtual Learning Environment (Online) | € 2,250.00 | |
15.04. - 16.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.04. - 18.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.04. - 21.04.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
22.04. - 23.04.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
24.04. - 25.04.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.04. - 30.04.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.04. - 29.04.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.04. - 02.05.2025 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
21.06. - 21.06.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
30.06. - 30.06.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
30.06. - 04.07.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
30.06. - 01.07.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
01.07. - 02.07.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.07. - 04.07.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
07.07. - 09.07.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
07.07. - 07.07.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
10.07. - 11.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
14.07. - 18.07.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
15.07. - 16.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.07. - 16.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.07. - 18.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.07. - 28.07.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.07. - 01.08.2025 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
28.07. - 30.07.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
22.08. - 23.08.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.09. - 13.09.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
29.09. - 29.09.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
30.09. - 01.10.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
02.10. - 03.10.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
06.10. - 08.10.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
07.10. - 08.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.10. - 10.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
13.10. - 17.10.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,259.00 | |
14.10. - 15.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
16.10. - 17.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.10. - 22.10.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.10. - 29.10.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.10. - 31.10.2025 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.10. - 27.10.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
29.10. - 30.10.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
30.10. - 31.10.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 |