Partial Reconfiguration Tools & Techniques

Course Description

This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.

This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both Ultrascale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.

Release Date

January 2018

Level

FPGA 4

Training Duration

2 days

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the AMD Xilinx design methodology and who have need of partial reconfiguration techniques

Prerequisites

• Essentials of FPGA Design course
• Vivado Static Timing Analysis and AMD Xilinx Design Constraints
• Advanced Tools and Techniques of the Vivado Design Suite
• Working HDL knowledge (VHDL or Verilog)

Software Tools

Vivado Design or System Edition 2016.1 with PR license

Skills Gained

After completing this comprehensive training, you will know how to:

• Build and assemble a Partially Reconfigurable system
• Define PR regions and reconfigurable modules with the PlanAhead software
• Generate the appropriate bitstreams targeting Platform Flash and System ACE™ interface tool files to support on-board partial bitstream storage
• Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
• Implement a PR system using the following techniques:
• Direct JTAG connection
• Floorplanning
• Timing constraints and analysis

Course Outline

Day 1

• Partial Reconfiguration Methodology
• Demo: Partial Reconfiguration Flow
• Partial Reconfiguration Tool Flow
• Lab 1: Partial Reconfiguration Flow
• Partial Reconfiguration Design Recommendations
• Lab 2: Floorplanning
• Optional: FPGA Configuration Overview
• Partial Reconfiguration Bitstreams

Day 2

• Demo: Partial Reconfiguration Controller (PRC) IP
• Lab 3: Using the PRC IP in Partial Reconfiguration Designs
• Managing Clocks, I/Os, and GTs
• Managing Timing
• Lab 4: Partial Reconfiguration Timing Analysis and Constraints
• Partial Reconfiguration in Embedded Systems
• Lab 5: Partial Reconfiguration in Embedded Systems
• Debugging Partial Reconfiguration Designs
• Lab 6: Using ILA Cores to Debug Partial Reconfiguration Designs

Lab Descriptions

• Lab 1: Partial Reconfiguration Flow – Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
• Lab 2: Floorplanning – Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
• Lab 3: Using the PRC IP in Partial Reconfiguration Designs – Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.
• Lab 4: Partial Reconfiguration Timing Analysis and Constraints – Shows how area groups and Reconfigurable Partitions affect design performance.
• Lab 5: Partial Reconfiguration in Embedded Systems – Illustrates implementing PR designs in an embedded environment.
• Lab 6: Using ILA Cores to Debug Partial Reconfiguration Designs – Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.