Admin >>
sologic logoCustomer login
  • so-logic
  • soopendays 2012
  • Activities
  • Knowledgebase
  • Trainings
  • IP Cores
  • Customers
  • Sitemap

Trainings

  • Search
  • Schedule
  • In-house Training
  • Create attendant account
  • Doulos
  • Mathworks
  • National Instruments
  • Silica
  • so-logic
  • Xilinx
    • Architecture
    • Connectivity
    • DSP
    • Embedded
    • Languages
    • Tools
      • Vivado Design Suite Tool Flow
      • Vivad Design Suite for ISE Software Project Navigator Users
      • Advanced Tools and Techniques of the Vivado Design Suite
      • Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
      • Vivado Static Timing Analysis and Xilinx Design Constraints
      • Designing with the Xilinx Analog Mixed Signal Solution
      • FPGA Power Optimization
      • Partial Reconfiguration Tools & Techniques
      • Essential Design with the PlanAhead Analysis and Design Tool
      • Advanced Design with the PlanAhead Analysis and Design Tool
      • Essentials of FPGA Design
      • Debugging Techniques Using the ChipScope Pro Tools
      • ISE Design Tool Flow
      • Advanced FPGA Implementation
      • Design Techniques for Lower Cost
      • Designing for Performance
  • Payment conditions
  • Shopping Cart
  • Instruction
Xilinx_atp_logo
Promo_tutorials
Promo_artix
Promo_zync
Promo_kintex
Promo_systemc
Promo_virtex

Tools

En 

Courses

  • Vivado Design Suite Tool Flow
  • Vivad Design Suite for ISE Software Project Navigator Users
  • Advanced Tools and Techniques of the Vivado Design Suite
  • Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
  • Vivado Static Timing Analysis and Xilinx Design Constraints
  • Designing with the Xilinx Analog Mixed Signal Solution
  • FPGA Power Optimization
  • Partial Reconfiguration Tools & Techniques
  • Essential Design with the PlanAhead Analysis and Design Tool
  • Advanced Design with the PlanAhead Analysis and Design Tool
  • Essentials of FPGA Design
  • Debugging Techniques Using the ChipScope Pro Tools
  • ISE Design Tool Flow
  • Advanced FPGA Implementation
  • Design Techniques for Lower Cost
  • Designing for Performance
Updated at: 2008-12-11 09:26↑ to the top
 
Questions or problems? support@so-logic.netLayout based on YAML, used encoding: utf-8