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• Baza znanja
  • FPGA univerzum
    • Uputstva
      • Basic FPGA Tutorial - Vivado VHDL v2024.1
      • Basic FPGA Tutorial - Vivado Verilog v2024.1
      • Basic FPGA Tutorial - ISE v14.7, VHDL
      • Basic Embedded System Design Tutorial v2024.1
      • Basic HLS Tutorial v2024.1
      • Basic SystemC Tutorial v2021.1
      • Basic Functional Verification Tutorial v2024.1
      • VHDL Style Guide
  • Linkovi
    • Elektronika2009-11-26 13:40:08 +0100
    • FPGA
    • Korisni linkovi2009-11-26 14:04:11 +0100
  • Kratka referentna uputstva
  • Newsletters
    • Newsletter - September 2016
    • Newsletter - February 2016
    • Newsletter - November 2015
    • Newsletter - May 2015
    • Newsletter - March 2015
• Kursevi
  • Xilinx
    • AI
      • Designing with Versal AI Engine 1: Architecture and Design Flow
      • Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
      • Designing with Versal AI Engine 3: Kernel Programming and Optimization
      • Developing AI Inference Solutions with the Vitis AI Platform
    • Architecture
      • Versal
        • Designing with the Versal Adaptive SoC: Architecture
        • Designing with the Versal Adaptive SoC: Design Methodology
        • Designing with the Versal Adaptive SoC: Power and Board Design
        • Designing with the Versal Adaptive SoC: Memory Interfaces
        • Designing with the Versal Adaptive SoC: Hardware Debug
      • Designing with the UltraScale and UltraScale+ Architectures
      • Designing with AMD Xilinx 7 Series Families
      • Legacy
        • Designing with Spartan-6 and Virtex-6 Families
        • Spartan-6 with ISE Migration to 7 Series with Vivado
        • Designing with the Virtex-5 LX , SX LXT, SXT Platform FPGA
        • Designing with the Virtex-4 Family
      • Versal Live Online Workshop Compendium Complete
        • AMD Versal Compendium 1 : Architecture
        • AMD Versal Compendium 2 : High Speed Communication
        • AMD Versal Compendium 3 : AI Engine
    • Connectivity
      • Designing with the Versal Adaptive SoC: Serial Transceivers
      • Designing with the Versal Adaptive SoC: PCI Express Systems
      • Designing with the Versal Adaptive SoC: Network on Chip
      • Designing with the Zynq UltraScale+ RFSoC
      • How to Design a High-Speed Memory Interface
      • PCIe Protocol Overview
      • Designing a LogiCORE PCI Express System
      • Designing with Multi-Gigabit Serial I/O
      • Gigabit Ethernet
      • Signal Integrity and Board Design for AMD Xilinx FPGAs
      • Designing with AMD Xilinx Serial Transceivers
    • DSP
      • High-Level Synthesis with Vitis HLS
      • Vitis Model Composer: A MATLAB and Simulink-based Product
      • C++ for Adaptive SOC
      • DSP Implementation Techniques for Xilinx FPGAs
      • Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework
    • Embedded
      • Adaptive SoCs for System Architects
      • Embedded Heterogeneous Design
      • Operating Systems and Hypervisors in Adaptive SoCs
      • Zynq UltraScale+ MPSoC: Boot and Platform Management
      • Zynq UltraScale+ MPSoC for the Hardware Designer
      • Zynq All Programmable SoC System Architecture
      • Migrating to the Vitis Unified IDE
      • Embedded Design with PetaLinux Tools
      • Embedded Systems Development
      • Embeded Systems Software Development
      • Accelerating Applications with the Vitis Unified Software Environment
    • HDL
      • Introduction to VHDL
      • Advanced VHDL
      • Introduction to Verilog
      • Designing with System Verilog
      • Verification with System Verilog
    • Tools
      • Designing with the IP Integrator Tool
      • Designing FPGAs Using the Vivado Design Suite 1
      • Designing FPGAs Using the Vivado Design Suite 2
      • Designing FPGAs Using the Vivado Design Suite 3
      • Designing FPGAs Using the Vivado Design Suite 4
      • UltraFast Design Methodology
      • Design Closure Techniques
      • DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
  • Doulos
  • Mathworks
    • MATLAB Grundlagen
    • Machine Learning mit MATLAB
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    • Programmierung von AMD Xilinx Zynq SoCs mit MATLAB und Simulink
    • Simulink zur System- und Algorithmenmodellierung
    • Signalverarbeitung mit Simulink
    • Objektorientierte Programmierung mit MATLAB
  • National Instruments
  • so-logic
    • Design Compendium Yocto for AMD Xilinx devices
    • Design Compendium Embedded System for AMD Xilinx devices
    • Design Compendium Verification for AMD Xilinx devices
    • Design Compendium VHDL for AMD Xilinx devices
    • Design Compendium System Verilog for AMD Xilinx devices
    • Design Compendium High Level Synthesis for AMD Xilinx devices
    • Design Compendium High Level SystemC for AMD Xilinx devices
    • High Level Synthesis
      • C++
      • SystemC TLM
      • SystemC Concepts
  • Uslovi plaćanja
  • Uputstva
• IP Cores
  • Interface Cores
    • Ethernet
      • 10/100/1000 Mb/s Ethernet
        • 10/100/1000 Mb/s MAC Controller Core
        • 1000BASE-X PCS Core
        • 10/100/1000 Mb/s MAC Configurator Core
        • Ethernet GMII Core
        • Ethernet GMII2MII Core
        • Ethernet GMII2RGMII Core
      • 10G Ethernet
        • 10G MAC Controller Core
        • 10GBASE-R PCS Core
        • 10 Gb/s Ethernet MAC Configurator Core
      • Utility Ethernet Cores
        • Ethernet Pause Generator Core
        • Generator Checker Core
      • Encryption Ethernet Cores
        • AES Core
      • Miscellaneous Ethernet Cores
        • ARP Decoder Core
        • ARP Encoder Core
        • ARP Packet Core
        • ARP Table Core
        • Capture Register Core
        • Error Statistics Core
        • Ethernet Encoder Core
        • Ethernet Decoder Core
        • ICMP Decoder Core
        • ICMP Encoder Core
        • IP Decoder Core
        • IP Encoder Core
        • Ethertype2dest Core
        • Network Packet FIFO Core
        • Port2tdest Core
        • Protocol2tdest Core
        • Tdest2ethertype Core
        • Tdest2port Core
        • Protocol2protocol Core
        • Time Stamp Counter Core
        • UDP Decoder Core
        • UDP Encoder Core
        • UDP Register Handler Core
    • Serial ATA
      • SATA-II Host Controller Core
      • SATA-III Host Controller Core
  • Machine Learning Cores
    • Ensemble Classifiers Cores
      • Ensemble Inference Cores
        • Decision Tree Ensemble Inference Core
      • Ensemble Evaluation Cores
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture
      • Combination Rules Cores
        • Behavior Knowledge Space Core - Parallel Architecture
        • Behavior Knowledge Space Core - Serial Architecture
        • Weighted Majority Voting Core - Parallel Architecture
        • Majority Voting Core - Parallel Architecture
        • Majority Voting Core - Serial Architecture
    • Decision Trees Cores
      • Decision Tree Inference Core
      • Decision Tree Core using Serial Architecture
      • Decision Tree Core using Pipelined Architecture
  • Processor and Microcontroller Cores
    • 8051 Microcontroller Cores
  • Finished and IP Cores Under Development
• Klijenti