IP Decoder Core |
Index
General Description
Supported FPGA Families and Development Tools
Applications
Deliverables
Licensing
Pricing and Additional Information
General Description
IP Decoder Core decodes the iPv4 header and compares the calculated checksum with the header checksum. The IP Decoder only pass through valid bytes in case if the MAC core adds padding to the frame.
The existing IEEE Std. 802.3-2008 standard is applicable to the Ethernet MAC core, including IP Decoder core.
The so_ip_ip_decoder core can be evaluated using Xilinx Evaluation Platforms before actual pur- chase. This is achieved by using a demonstration bit files for KC705 platform that allows the user to connect the So-Logic's complete 1G Ethernet solution system to some other Ethernet enabled device (PC or some Ethernet tester equipment) and evaluate system performance under different transfer scenarios.
Supported FPGA Families and Development Tools
IP Decoder core currently supports following Xilinx FPGA device familes:
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Spartan-6
- Virtex-5
IP Decoder core currently supports following Xilinx development tools:
- Xilinx Vivado Design Suite
Applications
- LAN networking
- Industrial Ethernet
- Distributed Storage Area Networks
- Cloud computing
Deliverables
Source code (source code license only)
- VHDL Source Code
VHDL test bench environment
- Tests with reference responses
Technical documentation
- Datasheet
- Installation notes
- User manual
Instantiation templates
Example application
Technical support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
Licensing
Netlist License
- Post-synthesis netlist
- Self checking testbench
- Test vectors for testing the core
- Place&Route scripts
- Constraints
- Instantiation templates
- Documentation
VHDL Source License
- VHDL RTL source code
- Complete verification plan together with the functional verification environment to verify the correct operation of the core
- Self checking testbench
- Vectors for testing the functionality of the core
- Simulation & synthesis scripts
- Documentation
Pricing and Additional Information
Pricing of IP Decoder core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the IP Decoder core, please contact So-Logic at:
Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44
email: ip_ethernet@so-logic.net