Weighted Majority Voting Core - Parallel Architecture
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classification of the instance based on the classifications supplied by the ensemble members. Ensemble members whose classifications are being combined can be of any type, decision trees, neural networks, support vector machines, or some other predictive models. Even more, the ensemble can be even composed from a mixture of different predictive models.
So_ip_ecr_mvt_p core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for all ensemble members in parallel. Using these classifications, so_ip_ecr_mvt_p core can calculate the combined classification of the current instance in parallel, to achieve the fastest classification speed.
So_ip_ecr_mvt_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mvt_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mvt_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
For more information about the so_ip_ecr_mvt_p core please consult the corresponding datasheet.
- Implements Weighted Majority Voting combination rule that can be used to combine the classifications of individual ensemble members into one, collective classification
- Combination of individual members classifications is done in parallel, resulting in fast classification speed
- Ensemble members can be of any type, for example decision trees, neural networks, support vector machines, etc.
- Ensemble can be composed from a mixture of different predictive models
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
- Speech and handwriting recognition
- Computer vision
- Machine perception
- Pattern recognition
- Medical diagnosis
- Robot locomotion
Source code (source code license only)
- VHDL Source Code
VHDL verification environment
- Tests with reference responses
- Installation notes
- HDL core specification
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
- Post-synthesis netlist
- Self checking testbench
- Test vectors for testing the core
- Place&Route scripts
- Instantiation templates
VHDL Source License
- VHDL RTL source code
- Complete verification plan together with testbenches needed to verify correct operation of the core
- Self checking testbench
- Vectors for testing the functionality of the core
- Simulation & synthesis scripts
For more information about the So-Logic ensemble combination rule core, please see the following datasheet:
- so_ip_ecr_mvt_p Datasheet
Reference design for the so_ip_ecr_mvt_p ensemble combination rule core is avaiable upon the request. Reference design comes in a form of bit file for user specified platform. Using this reference design, customer can evaluate the functionality and performance of the core for limited period of time. For more information about the reference design, please contact So-Logic at email@example.com.
Pricing of so_ip_ecr_mvt_p ensemble combination core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the so_ip_ecr_mvt_p ensemble combination core, please contact So-Logic at:
Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44