Decision Tree Core using Serial Architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware. It uses a simple sequential architecture that allows the smallest possible DT hardware implementation.
So_ip_edt_un core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edt_un design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edt_un core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
For more information about the so_ip_edt_un core please consult the corresponding datasheet.
- Implements DTs with previously defined structure
- Uses simple sequential architecture that allows the smallest possible DT hardware implementation
- Supports classification problems that are defined by numerical attributes only
- DTs with univariate or multivariate tests are supported
- DTs with nonlinear tests are supported
- Possibility to alter the implemented DT structure during the actual operation
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
- User can specify the number format for all DT parameters in order to achieve the best performance/size ratio after implementation
- Speech and handwriting recognition
- Computer vision
- Machine perception
- Pattern recognition
- Medical diagnosis
- Robot locomotion
Source code (source code license only)
- VHDL Source Code
VHDL verification environment
- Tests with reference responses
- Installation notes
- HDL core specification
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
- Post-synthesis netlist
- Self checking testbench
- Test vectors for testing the core
- Place&Route scripts
- Instantiation templates
VHDL Source License
- VHDL RTL source code
- Complete verification plan together with testbenches needed to verify correct operation of the core
- Self checking testbench
- Vectors for testing the functionality of the core
- Simulation & synthesis scripts
For more information about the So-Logic decision tree core, please see the following datasheet:
- so_ip_edt_un Datasheet
Reference design for the so_ip_edt_un decision tree core is avaiable upon the request. Reference design comes in a form of bit file for user specified platform. Using this reference design, customer can evaluate the functionality and performance of the core for limited period of time. For more information about the reference design, please contact So-Logic at firstname.lastname@example.org.
Pricing of so_ip_edt_un decision tree core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the so_ip_edt_un decision tree core, please contact So-Logic at:
Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44