Table
of Contents
Verilog 3
1Module 3
2Data Types
Declarations 3
2.1Register 3
2.2Net 3
2.3Other 3
3Task Declaration 4
4Function Declaration 4
5Parallel Statements 4
6Gated Primitives 4
7Sequential Statements 5
8Specify Block 6
8.1Specify Block
Statements 6
9Expression 6
9.1Binary Operators 6
9.2Unary Operators 7
9.3Size of Expression 7
10System Task 7
10.1Input 8
10.2Output 8
10.3Time 8
10.4Simulation Control 8
10.5Miscellaneous 9
10.6Escape
Sequences in Format Strings 9
11Lexical Elements 10
12Example 10
Verilog
1Module
2Data Types Declarations
2.1Register
2.2Net
2.3Other
3Task
Declaration
4Function
Declaration
5Parallel
Statements
6Gated
Primitives
7Sequential
Statements
8Specify
Block
8.1Specify Block Statements
9Expression
9.1Binary Operators
9.2Unary Operators
9.3Size of Expression
10System
Task
10.1Input
10.2Output
10.3Time
10.4Simulation Control
10.5Miscellaneous
10.6Escape Sequences in Format Strings
11Lexical
Elements
12Example
