A 2-day intermediate level course that will enable engineers with basic HDL knowledge to optimise their design implementation using VHDL or Verilog® for Xilinx Virtex™ Series and Spartan™ Series FPGAs. It combines a rapid introduction to the Xilinx FPGA architectures and Design Impementation tools, and the associated HDL design flow. The course contains a detailed exploration of how to achieve performance and utilisation goals for a wide variety of design functions.
An intensive class, this course offers one-stop training for all the tool and technology specifics for a Xilinx FPGA design. 50% of course time is devoted to practical workshops providing hands-on design practice using the Xilinx ISE Logic Design software and leading third-party simulators and synthesis tools.
The Xilinx TechClass supports the following Xilinx FPGAs:
- Virtex Series
- Spartan Series
The course is also suitable for engineers using earlier FPGA families, although the emphasis is on Xilinx's current FPGA families. Please note that the following are not covered in the Xilinx TechClass: the CoolRunner series and XC9500 CPLDs; embedded software design for Virtex-II Pro devices; RopcketIO MGT, the MicroBlaze soft processor; and System Generator for DSP.
Please note that the course is only available for delivery outside the UK and Republic of Ireland.
Who should attend?
Design engineers with a basic working knowledge of writing VHDL or Verilog for synthesis for ASIC, or other programmable device architectures, who:
- Are targeting a new design at Xilinx FPGA and require rapid familiarisation with the salient features of the architecture and software tools, or
- Are evaluating the migration of an existing design to a Xilinx FPGA, or
- Need to enhance their generic VHDL application skills in a technology-specific context, or
- Need to ensure that their HDL design skills and technology knowledge are fully developed to achieve speed and area goals for the Xilinx-based designs
What will you learn?
- The architectural features of Xilinx FPGAs
- How to exploit these features using VHDL or Verilog
- How to use synthesis tools and the Xilinx ISE Design Implementation software to meet your design requirements
- The practicalities of the complete programmable device design flow using HDLs, from entry through synthesis and place and route to back-annotation, timing analysis and device programming
Engineers must have attended at least the Doulos Introduction to VHDL course (which comprises the first 2 days of the Comprehensive VHDL course) or Verilog equivalent. Prior attendance of the Doulos Comprehensive VHDL or Comprehensive Verilog course is recommended. No prior knowledge of Xilinx FPGAs or design implementation software is required.
The focus of the Xilinx TechClass is the Xilinx ISE tools, including ModelSim XE, XST and Xilinx's Design Implementation tools. The Xilinx TechClass also supports the following synthesis tools:
- Mentor Graphics® LeonardoSpectrum™ and Precision™ RTL Synthesis
- Synplicity® Synplify® and Synplify Pro®
- Synopsys® DC-FPGA
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and had made them sought after resources in their own right. Course fees include:
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos VHDL or Verilog Golden Reference Guide for language, syntax, semantics and tips
- Tool tour guides (to support the design tools chosen from the above list)
Structure and Content
FPGA and Design Flow Overview
- Introduction to the main architectural features of Xilinx FPGAs and the ISE software
- The FPGA design flow using the ISE Project Navigator, including running synthesis, entering basic constraints and running the design implementation tools
- Basic timing constraints (PERIOD and OFFSET)
- Review of synchronous design techniques
- Using flip-flops in Xilinx FPGAs
- Pipelining and pipeline retiming
- Designing state machines
- Device reset
- Keeping the hierarchy
- Using IOB registers
Using FPGA Features
- Inference vs. instantiation
- Specialised FPGA features, including MUXFx, MUXCY, SRL16, BUFGMUX and IO Standards; how to use these in VHDL and Verilog designs
- Using components from the UNISIM library
- IO Standards and the Constraints Editor
- Interpreting the design implementation reports about design usage
Using Intellectual Property
- Distributed and block RAMs
- Virtex block RAM and FIFOs
- Manually placing block RAMs using PACE
- Using the Xilinx CORE Generator System
- Memory initialisation
Gate Level Simulation
- The SIMPRIM library
- Creating gate-level netlists and SDF files using the Project Navigator
- Managing RTL and gate-level simulations
- How to run gate-level simulations with SDF delays
- How to achieve timing closure for an FPGA design
- Understanding timing constraints, including time groups and multi-cycle clock constraints
- Constraints entry: the Constraints Editor and UCF files
- Using the Timing Analyzer to locate and diagnose timing problems
Advanced Clocking Techniques
- The features of Digital Clock Managers (DCMs) and how to use them
- Using the Architecture Wizard to configure a DCM
- Advanced timing constraints
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